1. Field of the Invention
The present invention relates to a semiconductor device including a logic circuit configured by MOS transistors, and particularly relates to a semiconductor device including an inverter circuit driven by two-way power supply wiring system in a semiconductor memory device such as a DRAM (Dynamic Random Access Memory).
2. Description of the Related Art
In recent years, semiconductor memory devices such as DRAMs have been often installed in mobile devices, and it becomes an important issue to reduce consumption current in standby operation. For the purpose of such a reduction in consumption current, a circuit configuration capable of suppressing sub-threshold current of MOS transistors using power supply wiring for supplying a sub-power supply voltage and a sub-ground voltage in addition to power supply wiring for supplying a power supply voltage and a ground voltage. By employing such a circuit configuration in a multi-stage inverter circuit or the like in DRAM, the reduction in consumption current can be expected in standby operation (for example, see Japanese Laid-Open Patent Publication H11-31385).
For example, a case in which four-stage inverter circuits as shown in FIGS. 16A and 16B are configured in a semiconductor device will be described. Here, two types of configuration having different connections to power supply wiring are assumed, and respective four-stage inverter circuits to which a power supply line voltage VCC, a ground voltage VSS, a sub-power supply voltage VCT and a sub-ground voltage VST are supplied are shown. First, FIG. 16A shows a configuration of the inverter circuit in which an output signal OUT is high in standby operation. In this configuration, the sub-power supply voltage VCT and the ground voltage VSS are supplied to odd number stage inverters, and the power supply voltage VCC and the sub-ground voltage VST are supplied to even number stage inverters. Meanwhile, FIG. 16B shows a configuration of the inverter circuit in which the output signal OUT is low in standby operation. In this configuration, the power supply voltage VCC and the sub-ground voltage VST are supplied to odd number inverters, and the sub-power supply voltage VCT and the ground voltage VSS are supplied to even number stage inverters, so that the connections of the power supply wiring is reverse to those in FIG. 16A.
A circuit configuration to realize the above-described inverter circuit is shown, for example, in FIG. 1 (A detailed description of FIG. 1 will be described later.) corresponding to FIG. 16B. Respective inverters forming an inverter unit 1 of FIG. 1 includes a pair of a PMOS transistor and an NMOS transistor. Drivers 2 and 3 are controlled by control voltages Vgp and Vgn, the power supply voltage VCC and the ground voltage VSS are supplied to a MOS transistor being on, and the sub-power supply voltage VCT and the sub-ground voltage VST are supplied to a MOS transistor being off. Thereby, it is possible to suppress unnecessary sub-threshold current.
FIG. 17 shows a general layout corresponding to the circuit configuration of FIG. 1. The layout of FIG. 17 includes diffusion layers 101 to 107 in which PMOS transistors P1 to P7 are respectively formed, diffusion layers 111 to 117 in which NMOS transistors N1 to N7 are respectively formed. Further, a gate wiring layer 121 connected to each gate electrode of the MOS transistors, a source/drain wiring layer 122 in which wiring for each source/drain of the MOS transistors is formed, and a wiring layer 123 in which various kinds of wiring for the power supply or for controlling are formed are stacked. The wiring layer 123 includes a main power supply line L1 for supplying the power supply voltage VCC, a sub-power supply line L3 for supplying the sub-power supply voltage VCT, a main ground line L2 for supplying the ground voltage VSS, and a sub-ground line L4 for supplying the sub-ground voltage VST. Further, the source/drain wiring layer 122 and the wiring layer 123 are connected by vias 124 in a stacking direction. In this manner, by changing positions of the vias 124 in the manufacturing process for respective lines extending in parallel in the wiring layer 123 at both sides of the diffusion layers 101 to 107 and 111 to 117, each MOS transistor is connected to a desired line so as to realize the circuit configuration of FIG. 1.
However, in the wiring layer 123 in the layout of FIG. 17, total six lines including the main power supply line L1, the main ground line L2, the sub-power supply line L3, the sub-ground line L4 and driver control lines L5 and L6 are arranged in parallel. In this case, in consideration of positions of the vias 124 and the source/drain wiring layer 122, it is inevitable that respective sets of three lines are arranged on both the P-channel and N-channel sides between which the diffusion layers 101 to 107 and 111 to 117 are disposed, and thereby increasing extra layout area. If only the power supply voltage VCC and the ground voltage VSS are used as the power supply wiring, only two lines including the main power supply line L1 and the main ground line L2 are required. However, the circuit configuration using two-way power supply wiring system is adopted, and thus the extra layout area for arranging four lines in parallel including the sub-power supply line L3, the sub-ground line L4 and the driver control lines L5 and L6 is required. Further, in FIG. 17, a space in which the diffusion layers 101 to 104 and 111 to 114 forming the inverter unit 1 are arranged separately from the diffusion layers 105 to 107 and 115 to 117 forming drivers 2 and 3 is required, and the layout area occupied by the drivers 2 and 3 is not negligible.
In this manner, when employing the configuration capable of reducing consumption current in standby operation, it is a problem that the area for arranging the lines and the like in a layout of the semiconductor device is inevitably increased and the entire chip size is increased.